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| M Features * * * * * * * * * * * * * * * 10-bit resolution 1 LSB max DNL 1 LSB max INL 4 (MCP3004) or 8 (MCP3008) input channels Analog inputs programmable as single-ended or pseudo-differential pairs On-chip sample and hold SPI serial interface (modes 0,0 and 1,1) Single supply operation: 2.7V - 5.5V 200 ksps max. sampling rate at V DD = 5V 75 ksps max. sampling rate at VDD = 2.7V Low power CMOS technology 5 nA typical standby current, 2 A max. 500 A max. active current at 5V Industrial temp range: -40C to +85C Available in PDIP, SOIC and TSSOP packages MCP3004/3008 Description The Microchip Technology Inc. MCP3004/3008 devices are successive approximation 10-bit Analogto-Digital (A/D) converters with on-board sample and hold circuitry. The MCP3004 is programmable to provide two pseudo-differential input pairs or four singleended inputs. The MCP3008 is programmable to provide four pseudo-differential input pairs or eight singleended inputs. Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) are specified at 1 LSB. Communication with the devices is accomplished using a simple serial interface compatible with the SPI protocol. The devices are capable of conversion rates of up to 200 ksps. The MCP3004/3008 devices operate over a broad voltage range (2.7V - 5.5V). Low current design permits operation with typical standby currents of only 5 nA and typical active currents of 320 A. The MCP3004 is offered in 14-pin PDIP, 150 mil SOIC and TSSOP packages, while the MCP3008 is offered in 16pin PDIP and SOIC packages. 2.7V 4-Channel/8-Channel 10-Bit A/D Converters with SPITM Serial Interface Applications * * * * Sensor Interface Process Control Data Acquisition Battery Operated Systems Functional Block Diagram VREF CH0 CH1 CH7* 14 13 12 11 10 9 8 VDD VREF AGND CLK DOUT DIN CS/SHDN Sample and Hold Control Logic Input Channel Max VDD VSS Package Types PDIP, SOIC, TSSOP CH0 CH1 CH2 CH3 NC NC DGND 1 2 3 4 5 6 7 DAC Comparator 10-Bit SAR MCP3004 Shift Register DOUT CS/SHDN DIN CLK PDIP, SOIC CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD VREF AGND CLK DOUT DIN CS/SHDN DGND * Note: Channels 4-7 available on MCP3008 Only 2002 Microchip Technology Inc. MCP3008 DS21295B-page 1 MCP3004/3008 1.0 ELECTRICAL CHARACTERISTICS PIN FUNCTION TABLE Name VDD DGND AGND CH0-CH7 CLK DIN DOUT CS/SHDN VREF Function +2.7V to 5.5V Power Supply Digital Ground Analog Ground Analog Inputs Serial Clock Serial Data In Serial Data Out Chip Select/Shutdown Input Reference Voltage Input Absolute Maximum Ratings* VDD ........................................................................7.0V All inputs and outputs w.r.t. VSS .....-0.6V to VDD +0.6V Storage temperature .......................... -65C to +150C Ambient temp. with power applied ..... -65C to +125C Soldering temperature of leads (10 seconds) .. +300C ESD protection on all pins .................................. > 4 kV *Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at V DD = 5V, V REF = 5V, TAMB = -40C to +85C, fSAMPLE = 200 ksps and fCLK = 18*fSAMPLE. Unless otherwise noted, typical values apply for VDD = 5V, TAMB = 25C. Parameter Conversion Rate Conversion Time Analog Input Sample Time Throughput Rate DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Dynamic Performance Total Harmonic Distortion Signal to Noise and Distortion (SINAD) Spurious Free Dynamic Range Reference Input Voltage Range Current Drain 0.25 -- -- 100 0.001 VDD 150 3 V A A Note 2 CS = VDD = 5V -- -- -- -76 61 78 dB dB dB VIN = 0.1V to 4.9V@1 kHz VIN = 0.1V to 4.9V@1 kHz VIN = 0.1V to 4.9V@1 kHz INL DNL -- -- -- -- 10 0.5 0.25 -- -- 1 1 1.5 1.0 bits LSB LSB LSB LSB No missing codes over temperature tCONV tSAMPLE fSAMPLE -- -- -- 1.5 -- 200 75 10 clock cycles clock cycles ksps ksps VDD = VREF = 5V VDD = VREF = 2.7V Sym Min Typ Max Units Conditions Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to VREF levels. 3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2, "Maintaining Minimum Clock Speed", for more information. DS21295B-page 2 2002 Microchip Technology Inc. MCP3004/3008 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at V DD = 5V, V REF = 5V, TAMB = -40C to +85C, fSAMPLE = 200 ksps and fCLK = 18*fSAMPLE. Unless otherwise noted, typical values apply for VDD = 5V, TAMB = 25C. Parameter Analog Inputs Input Voltage Range for CH0 or CH1 in Single-Ended Mode Input Voltage Range for IN+ in pseudo-differential mode Input Voltage Range for IN- in pseudo-differential mode Leakage Current Switch Resistance Sample Capacitor Digital Input/Output Data Coding Format High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Output Leakage Current Pin Capacitance (All Inputs/Outputs) Timing Parameters Clock Frequency Clock High Time Clock Low Time CS Fall To First Rising CLK Edge CS Fall To Falling CLK Edge Data Input Setup Time Data Input Hold Time CLK Fall To Output Data Valid CLK Fall To Output Enable CS Rise To Output Disable CS Disable Time DOUT Rise Time DOUT Fall Time fCLK tHI tLO tSUCS tCSD tSU tHD tDO tEN tDIS tCSH tR tF -- 125 125 100 -- -- -- -- -- -- 270 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 3.6 1.35 -- -- -- 0 50 50 125 200 125 200 100 -- 100 100 MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns See Test Circuits, Figure 1-2 (Note 1) See Test Circuits, Figure 1-2 (Note 1) VDD = 5V, See Figure 1-2 VDD = 2.7V, See Figure 1-2 VDD = 5V, See Figure 1-2 VDD = 2.7V, See Figure 1-2 See Test Circuits, Figure 1-2 VDD = 5V (Note 3) VDD = 2.7V (Note 3) VIH VIL VOH VOL ILI ILO CIN, COUT 4.1 -- -10 -10 -- Straight Binary 0.7 VDD -- -- -- -- -- -- -- -- 0.3 VDD -- 0.4 10 10 10 V V V V A A pF IOH = -1 mA, VDD = 4.5V IOL = 1 mA, V DD = 4.5V VIN = VSS or VDD VOUT = VSS or VDD VDD = 5.0V (Note 1) TAMB = 25C, f = 1 MHz VSS INVSS-100 -- -- -- -- -- -- 0.001 1000 20 VREF VREF+INVSS+100 1 -- -- mV A pF See Figure 4-1 See Figure 4-1 V Sym Min Typ Max Units Conditions Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to VREF levels. 3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2, "Maintaining Minimum Clock Speed", for more information. 2002 Microchip Technology Inc. DS21295B-page 3 MCP3004/3008 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at V DD = 5V, V REF = 5V, TAMB = -40C to +85C, fSAMPLE = 200 ksps and fCLK = 18*fSAMPLE. Unless otherwise noted, typical values apply for VDD = 5V, TAMB = 25C. Parameter Power Requirements Operating Voltage Operating Current VDD IDD 2.7 -- -- 425 225 5.5 550 V A VDD = VREF = 5V, DOUT unloaded VDD = VREF = 2.7V, DOUT unloaded CS = VDD = 5.0V Sym Min Typ Max Units Conditions Standby Current Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistance Thermal Resistance, 14L-PDIP Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP Thermal Resistance, 16L-PDIP Thermal Resistance, 16L-SOIC IDDS TA TA TA JA JA JA JA JA -- -40 -40 -65 -- -- -- -- -- 0.005 -- -- -- 70 108 100 70 90 2 +85 +85 +150 -- -- -- -- -- A C C C C/W C/W C/W C/W C/W Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to VREF levels. 3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2, "Maintaining Minimum Clock Speed", for more information. TCSH CS TSUCS THI TLO CLK TSU DIN THD MSB IN TEN TDO NULL BIT MSB OUT TR TF TDIS LSB DOUT FIGURE 1-1: Serial Interface Timing. DS21295B-page 4 2002 Microchip Technology Inc. MCP3004/3008 1.4V 3 k DOUT CL = 100 pF Test Point VDD Test Point DOUT 100 pF VSS 3 k VDD /2 tDIS Waveform 2 tEN Waveform tDIS Waveform 1 Voltage Waveforms for tR , tF D OUT tR tF VOH VOL CS CLK Voltage Waveforms for tDO DOUT CLK tDO DOUT Voltage Waveforms for tEN 1 2 3 4 B9 tEN Voltage Waveforms for tDIS CS VIH 90% TDIS DOUT Waveform 2 * Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is low, unless disabled by the output control. 10% FIGURE 1-2: Load Circuit for tR, tF, tDO. DOUT Waveform 1* FIGURE 1-3: Load circuit for tDIS and tEN. 2002 Microchip Technology Inc. DS21295B-page 5 MCP3004/3008 2.0 Note: TYPICAL PERFORMANCE CHARACTERISTICS The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VDD = VREF = 5V, fCLK = 18* fSAMPLE, TA = 25C. 1.0 0.8 0.6 0.4 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 25 50 75 100 125 150 175 200 225 250 0 25 50 75 100 Negative INL Positive INL VDD = VREF = 2.7 V INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 Negative INL Sample Rate (ksps) INL (LSB) Positive INL Sample Rate (ksps) FIGURE 2-1: Sample Rate. Integral Nonlinearity (INL) vs. FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V). INL(LSB) 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1 1.0 0.8 0.6 Positive INL 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 2 3 4 5 6 0.0 0.5 1.0 1.5 Negative INL Positive INL VDD = VREF = 2.7 V fSAMPLE = 75 ksps Negative INL INL(LSB) 2.0 2.5 3.0 VREF (V) VREF (V) FIGURE 2-2: VREF. 0.5 0.4 0.3 0.2 Integral Nonlinearity (INL) vs. FIGURE 2-5: Integral Nonlinearity (INL) vs. VREF (VDD = 2.7V). 0.5 VDD = VREF = 2.7 V fSAMPLE = 75 ksps VDD = VREF = 5 V fSAMPLE = 200 ksps 0.4 0.3 0.2 INL (LSB) INL (LSB) 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 0 128 256 384 512 640 768 896 1024 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 0 128 256 384 512 640 768 896 1024 Digital Code Digital Code FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part). FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V). DS21295B-page 6 2002 Microchip Technology Inc. MCP3004/3008 Note: Unless otherwise indicated, VDD = V REF = 5V, fCLK = 18* fSAMPLE, TA = 25C. 0.6 0.4 Positive INL 0.6 0.4 VDD = VREF = 2.7 V fSAMPLE = 75 ksps Positive INL INL (LSB) INL (LSB) 0.2 0.0 -0.2 Negative INL -0.4 -0.6 -50 -25 0 25 50 75 100 0.2 0.0 -0.2 -0.4 -0.6 -50 -25 0 Negative INL 25 50 75 100 Temperature (C) Temperature (C) FIGURE 2-7: Temperature. 0.6 0.4 Integral Nonlinearity (INL) vs. FIGURE 2-10: Integral Nonlinearity (INL) vs. Temperature (VDD = 2.7V). 0.6 0.4 VDD = VREF = 2.7 V DNL (LSB) DNL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 0 25 Positive DNL 0.2 0.0 -0.2 -0.4 -0.6 Positive DNL Negative DNL Negative DNL 50 75 100 125 150 175 200 225 250 0 25 50 75 100 Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-8: Differential Nonlinearity (DNL) vs. Sample Rate. FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate (VDD = 2.7V). 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1 2 3 4 5 Negative DNL Positive DNL 0.8 0.6 0.4 Positive DNL VDD = VREF = 2.7 V fSAMPLE = 75 ksps DNL (LSB) DNL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Negative DNL VREF (V) VREF(V) FIGURE 2-9: vs. VREF. Differential Nonlinearity (DNL) FIGURE 2-12: Differential Nonlinearity (DNL) vs. VREF (VDD = 2.7V). 2002 Microchip Technology Inc. DS21295B-page 7 MCP3004/3008 Note: Unless otherwise indicated, VDD = V REF = 5V, fCLK = 18* fSAMPLE, TA = 25C. 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 128 256 384 512 640 768 896 1024 VDD = VREF = 5 V fSAMPLE = 200 ksps 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 128 256 384 512 640 768 896 1024 VDD = VREF = 2.7 V fSAMPLE = 75 ksps DNL (LSB) Digital Code DNL (LSB) Digital Code FIGURE 2-13: Differential Nonlinearity (DNL) vs. Code (Representative Part). 0.6 0.4 Positive DNL FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part, VDD = 2.7V). 0.6 0.4 VDD = VREF = 2.7 V fSAMPLE = 75 ksps DNL (LSB) DNL (LSB) 0.2 0.0 -0.2 Negative DNL -0.4 -0.6 -50 -25 0 25 50 75 100 0.2 0.0 -0.2 -0.4 -0.6 -50 -25 0 Positive DNL Negative DNL 25 50 75 100 Temperature (C) Temperature (C) FIGURE 2-14: Differential Nonlinearity (DNL) vs. Temperature. FIGURE 2-17: Differential Nonlinearity (DNL) vs. Temperature (VDD = 2.7V). 2.0 1.5 VDD = 2.7 V fSAMPLE = 75 ksps 8 7 Offset Error (LSB) Gain Error (LSB) 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0 1 6 5 4 3 2 1 0 VDD = 2.7 V fSAMPLE = 75 ksps VDD = 5 V fSAMPLE = 200 ksps VDD = 5 V fSAMPLE = 200 ksps 2 3 4 5 0 1 2 3 4 5 VREF(V) VREF (V) FIGURE 2-15: Gain Error vs. VREF. FIGURE 2-18: Offset Error vs. VREF. DS21295B-page 8 2002 Microchip Technology Inc. MCP3004/3008 Note: Unless otherwise indicated, VDD = V REF = 5V, fCLK = 18* fSAMPLE, TA = 25C. 0.0 -0.1 V DD = VREF = 2.7 V f SAMPLE = 75 ksps 1.2 1.0 VDD = VREF = 5 V fSAMPLE = 200 ksps Offset Error (LSB) Gain Error (LSB) -0.2 -0.3 -0.4 -0.5 -0.6 -50 -25 0 25 50 75 100 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 100 VDD = VREF = 2.7 V fSAMPLE = 75 ksps VDD = VREF = 5 V fSAMPLE = 200 ksps Temperature (C) Temperature (C) FIGURE 2-19: Gain Error vs. Temperature. 80 70 60 VDD = VREF = 5 V f SAMPLE = 200 ksps FIGURE 2-22: Offset Error vs. Temperature. 80 70 60 VDD = VREF = 5 V fSAMPLE = 200 ksps SNR (dB) 50 40 30 20 10 0 1 10 100 VDD = VREF = 2.7 V fSAMPLE = 75 ksps SINAD (dB) 50 40 30 20 10 0 1 10 100 VDD = VREF = 2.7 V fSAMPLE = 75 ksps Input Frequency (kHz) Input Frequency (kHz) FIGURE 2-20: Signal to Noise (SNR) vs. Input Frequency. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 1 10 100 VDD = VREF = 5 V f SAMPLE = 200 ksps FIGURE 2-23: Signal to Noise and Distortion (SINAD) vs. Input Frequency. 70 60 SINAD (dB) THD (dB) VDD = VREF = 2.7 V fSAMPLE = 75 ksps 50 40 30 20 10 0 -40 VDD = VREF = 5 V fSAMPLE = 200 ksps VDD = VREF = 2.7 V fSAMPLE = 75 ksps -35 -30 -25 -20 -15 -10 -5 0 Input Frequency (kHz) Input Signal Level (dB) FIGURE 2-21: Total Harmonic Distortion (THD) vs. Input Frequency. FIGURE 2-24: Signal to Noise and Distortion (SINAD) vs. Input Signal Level. 2002 Microchip Technology Inc. DS21295B-page 9 MCP3004/3008 Note: Unless otherwise indicated, VDD = V REF = 5V, fCLK = 18* fSAMPLE, TA = 25C. 10.00 10.0 9.8 9.75 9.6 VDD = VREF = 2.7 V fSAMPLE = 75 ksps 9.4 9.2 9.0 8.8 8.6 8.4 8.2 2.5 3.0 3.5 4.0 4.5 5.0 8.0 1 10 100 VDD = VREF = 2.7 V fSAMPLE = 75 ksps VDD = VREF = 5 V fSAMPLE = 200 ksps ENOB (rms) 9.50 9.25 VDD = VREF = 5 V fSAMPLE = 200 ksps 9.00 0.0 0.5 1.0 1.5 2.0 VREF (V) ENOB (rms) Input Frequency (kHz) FIGURE 2-25: Effective Number of Bits (ENOB) vs. VREF. 100 90 80 70 60 50 40 30 20 10 0 1 10 100 VDD = VREF = 2.7 V fSAMPLE = 75 ksps FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency. VDD = VREF = 5 V fSAMPLE = 200 ksps Power Supply Rejection (dB) 0 -10 -20 -30 -40 -50 -60 -70 1 VDD = VREF = 5 V fSAMPLE = 200 ksps SFDR (dB) 10 100 1000 10000 Input Frequency (kHz) Ripple Frequency (kHz) FIGURE 2-26: Spurious Free Dynamic Range (SFDR) vs. Input Frequency. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 20000 40000 VDD = VREF = 5 V FSAMPLE = 200 ksps FINPUT = 10.0097 kHz 4096 points FIGURE 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 5000 VDD = VREF = 2.7 V fSAMPLE = 75 ksps fINPUT = 1.00708 kHz 4096 points Amplitude (dB) 60000 80000 100000 Amplitude (dB) Frequency (Hz) 10000 15000 20000 25000 30000 35000 Frequency (Hz) FIGURE 2-27: Frequency Spectrum of 10 kHz Input (Representative Part). FIGURE 2-30: Frequency Spectrum of 1 kHz Input (Representative Part, VDD = 2.7V). DS21295B-page 10 2002 Microchip Technology Inc. MCP3004/3008 Note: Unless otherwise indicated, VDD = V REF = 5V, fCLK = 18* fSAMPLE, TA = 25C. 550 500 450 400 350 300 250 200 150 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VREF = VDD All points at fCLK = 3.6 MHz except at VREF = VDD = 2.5 V, fCLK = 1.35 MHz 550 500 450 400 350 300 250 200 150 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VREF = VDD All points at fCLK = 3.6 MHz except at VREF = VDD = 2.5 V, f CLK = 1.35 MHz IDD (A) IDD (A) VDD (V) VDD (V) FIGURE 2-31: IDD vs. VDD. 500 450 400 350 FIGURE 2-34: IREF vs. VDD. 120 110 100 90 80 70 60 50 40 30 20 10 0 10 VDD = VREF = 5 V IDD (A) 300 250 200 150 100 50 0 10 VDD = VREF = 5 V IREF (A) VDD = VREF = 2.7 V V DD = VREF = 2.7 V 100 1000 10000 100 1000 10000 Clock Frequency (kHz) Clock Frequency (kHz) FIGURE 2-32: IDD vs. Clock Frequency. 550 500 450 400 350 300 250 200 150 100 50 0 -50 -25 0 25 50 75 100 VDD = VREF = 2.7 V fCLK = 1.35 MHz VDD = VREF = 5 V fCLK = 3.6 MHz FIGURE 2-35: IREF vs. Clock Frequency. 140 120 VDD = VREF = 5 V fCLK = 3.6 MHz I DD (A) IREF (A) 100 80 60 40 20 0 -50 -25 0 25 50 75 100 V DD = VREF = 2.7 V f CLK = 1.35 MHz Temperature (C) Temperature (C) FIGURE 2-33: IDD vs. Temperature. FIGURE 2-36: IREF vs. Temperature. 2002 Microchip Technology Inc. DS21295B-page 11 MCP3004/3008 Note: Unless otherwise indicated, VDD = V REF = 5V, fCLK = 18* fSAMPLE, TA = 25C. 70 60 50 2.0 Analog Input Leakage (nA) VREF = CS = VDD 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 VDD = VREF = 5 V IDDS (pA) 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) -50 -25 0 25 50 75 100 Temperature (C) FIGURE 2-37: IDDS vs. VDD. 100.00 V DD = VREF = CS = 5 V 10.00 FIGURE 2-39: Analog Input Leakage Current vs. Temperature. IDDS (nA) 1.00 0.10 0.01 -50 -25 0 25 50 75 100 Temperature (C) FIGURE 2-38: IDDS vs. Temperature. DS21295B-page 12 2002 Microchip Technology Inc. MCP3004/3008 3.0 PIN DESCRIPTIONS PIN FUNCTION TABLE Function +2.7V to 5.5V Power Supply Digital Ground Analog Ground Analog Inputs Serial Clock Serial Data In Serial Data Out Chip Select/Shutdown Input Reference Voltage Input Name VDD DGND AGND CH0-CH7 CLK DIN DOUT CS/SHDN VREF 4.0 DEVICE OPERATION TABLE 3-1: The MCP3004/3008 A/D converters employ a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the first rising edge of the serial clock once CS has been pulled low. Following this sample time, the device uses the collected charge on the internal sample and hold capacitor to produce a serial 10-bit digital output code. Conversion rates of 100 ksps are possible on the MCP3004/3008. See Section 6.2, "Maintaining Minimum Clock Speed", for information on minimum clock rates. Communication with the device is accomplished using a 4-wire SPIcompatible interface. 4.1 Analog Inputs 3.1 DGND Digital ground connection to internal digital circuitry. 3.2 3.3 AGND CH0 - CH7 Analog ground connection to internal analog circuitry. Analog inputs for channels 0 - 7, respectively, for the multiplexed inputs. Each pair of channels can be programmed to be used as two independent channels in single-ended mode or as a single pseudo-differential input where one channel is IN+ and one channel is IN. See Section 4.1, "Analog Inputs", and Section 5.0, "Serial Communication", for information on programming the channel configuration. The MCP3004/3008 devices offer the choice of using the analog input channels configured as single-ended inputs or pseudo-differential pairs. The MCP3004 can be configured to provide two pseudo-differential input pairs or four single-ended inputs. The MCP3008 can be configured to provide four pseudo-differential input pairs or eight single-ended inputs. Configuration is done as part of the serial command before each conversion begins. When used in the pseudo-differential mode, each channel pair (i.e., CH0 and CH1, CH2 and CH3 etc.) are programmed as the IN+ and IN- inputs as part of the command string transmitted to the device. The IN+ input can range from IN- to (VREF + IN-). The IN- input is limited to 100 mV from the VSS rail. The INinput can be used to cancel small signal commonmode noise, which is present on both the IN+ and INinputs. When operating in the pseudo-differential mode, if the voltage level of IN+ is equal to or less than IN-, the resultant code will be 000h. If the voltage at IN+ is equal to or greater than {[VREF + (IN-)] - 1 LSB}, then the output code will be 3FFh. If the voltage level at INis more than 1 LSB below VSS, the voltage level at the IN+ input will have to go below VSS to see the 000h output code. Conversely, if IN- is more than 1 LSB above VSS, the 3FFh code will not be seen unless the IN+ input level goes above VREF level. For the A/D converter to meet specification, the charge holding capacitor (CSAMPLE) must be given enough time to acquire a 10-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1. This diagram illustrates that the source impedance (RS) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to charge the capacitor (CSAMPLE). Consequently, larger source impedances increase the offset, gain and integral linearity errors of the conversion (see Figure 4-2). 3.4 Serial Clock (CLK) The SPI clock pin is used to initiate a conversion and clock out each bit of the conversion as it takes place. See Section 6.2, "Maintaining Minimum Clock Speed", for constraints on clock speed. 3.5 Serial Data Input (D IN) The SPI port serial data input pin is used to load channel configuration data into the device. 3.6 Serial Data Output (DOUT) The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place. 3.7 Chip Select/Shutdown (CS/SHDN) The CS/SHDN pin is used to initiate communication with the device when pulled low. When pulled high, it will end a conversion and put the device in low power standby. The CS/SHDN pin must be pulled high between conversions. 2002 Microchip Technology Inc. DS21295B-page 13 MCP3004/3008 4.2 Reference Input EQUATION 1024 x V IN Digital Output Code = -------------------------V REF VIN = analog input voltage VREF = reference voltage When using an external voltage reference device, the system designer should always refer to the manufacturer's recommendations for circuit layout. Any instability in the operation of the reference device will have a direct effect on the operation of the A/D converter. For each device in the family, the reference input (VREF) determines the analog input voltage range. As the reference input is reduced, the LSB size is reduced accordingly. EQUATION V REF LSB Size = -----------1024 The theoretical digital output code produced by the A/D converter is a function of the analog input signal and the reference input, as shown below. VDD CHx VT = 0.6V Sampling Switch SS RS = 1 k C SAMPLE = DAC capacitance = 20 pF VSS RSS VA CPIN 7 pF VT = 0.6V ILEAKAGE 1 nA Legend VA = Signal Source R SS = Source Impedance CHx = Input Channel Pad C PIN = Input Pin Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current At The Pin Due To Various Junctions SS = sampling switch RS = sampling switch resistor CSAMPLE = sample/hold capacitance FIGURE 4-1: Analog Input Model. 4 Clock Frequency (Mhz) VDD = VREF = 5 V fSAMPLE = 200 ksps 3 2 1 VDD = VREF = 2.7 V fSAMPLE = 75 ksps 0 100 1000 10000 Input Resistance (Ohms) FIGURE 4-2: Maximum Clock Frequency vs. Input resistance (RS) to maintain less than a 0.1 LSB deviation in INL from nominal conditions. DS21295B-page 14 2002 Microchip Technology Inc. MCP3004/3008 5.0 SERIAL COMMUNICATION TABLE 5-1: Communication with the MCP3004/3008 devices is accomplished using a standard SPI-compatible serial interface. Initiating communication with either device is done by bringing the CS line low (see Figure 5-1). If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first clock received with CS low and D IN high will constitute a start bit. The SGL/DIFF bit follows the start bit and will determine if the conversion will be done using single-ended or differential input mode. The next three bits (D0, D1 and D2) are used to select the input channel configuration. Table 5-1 and Table 5-2 show the configuration bits for the MCP3004 and MCP3008, respectively. The device will begin to sample the analog input on the fourth rising edge of the clock after the start bit has been received. The sample period will end on the falling edge of the fifth clock following the start bit. Once the D0 bit is input, one more clock is required to complete the sample and hold period (D IN is a "don't care" for this clock). On the falling edge of the next clock, the device will output a low null bit. The next 10 clocks will output the result of the conversion with MSB first, as shown in Figure 5-1. Data is always output from the device on the falling edge of the clock. If all 10 data bits have been transmitted and the device continues to receive clocks while the CS is held low, the device will output the conversion result LSB first, as is shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. If necessary, it is possible to bring CS low and clock in leading zeros on the DIN line before the start bit. This is often done when dealing with microcontroller-based SPI ports that must send 8 bits at a time. Refer to Section 6.1, "Using the MCP3004/3008 with Microcontroller (MCU) SPI Ports", for more details on using the MCP3004/3008 devices with hardware SPI ports. CONFIGURE BITS FOR THE MCP3004 Channel Selection CH0 CH1 CH2 CH3 CH0 = IN+ CH1 = INCH0 = INCH1 = IN+ CH2 = IN+ CH3 = INCH2 = INCH3 = IN+ Input Configuration Single/ D2* D1 D0 Diff 1 1 1 1 0 0 0 0 X X X X X X X X 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 single-ended single-ended single-ended single-ended differential differential differential differential Control Bit Selections * D2 is "don't care" for MCP3004 TABLE 5-2: Control Bit Selections Single /Diff 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CONFIGURE BITS FOR THE MCP3008 Input Configuration single-ended single-ended single-ended single-ended single-ended single-ended single-ended single-ended differential differential differential differential differential differential differential differential Channel Selection CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH0 = IN+ CH1 = INCH0 = INCH1 = IN+ CH2 = IN+ CH3 = INCH2 = INCH3 = IN+ CH4 = IN+ CH5 = INCH4 = INCH5 = IN+ CH6 = IN+ CH7 = INCH6 = INCH7 = IN+ D1 D0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2002 Microchip Technology Inc. DS21295B-page 15 MCP3004/3008 tCYC tCSH CS tSUCS CLK tCYC DIN Start D2 D1 D0 SGL/ DIFF Don't Care Start D2 SGL/ DIFF DOUT HI-Z Null Bit B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 * tCONV HI-Z tSAMPLE tDATA ** * After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output LSB first data, then followed with zeros indefinitely. See Figure 5-2 below. ** tDATA: during this time, the bias current and the comparator powers down while the reference input becomes a high impedance node. FIGURE 5-1: Communication with the MCP3004 or MCP3008. tCYC CS tSUCS CLK Start DIN D2 D1 D0 SGL/ DIFF HI-Z Don't Care Power Down tCSH DOUT HI-Z Null B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9* Bit (MSB) tSAMPLE tCONV tDATA ** * After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zeros indefinitely. ** tDATA: During this time, the bias circuit and the comparator powers down while the reference input becomes a high impedance node, leaving the CLK running to clock out LSB first data or zeroes. FIGURE 5-2: Communication with MCP3004 or MCP3008 in LSB First Format. DS21295B-page 16 2002 Microchip Technology Inc. MCP3004/3008 6.0 6.1 APPLICATIONS INFORMATION Using the MCP3004/3008 with Microcontroller (MCU) SPI Ports With most microcontroller SPI ports, it is required to send groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the rising edge. Because communication with the MCP3004/ 3008 devices may not need multiples of eight clocks, it will be necessary to provide more clocks than are required. This is usually done by sending `leading zeros' before the start bit. As an example, Figure 6-1 and Figure 6-2 shows how the MCP3004/3008 can be interfaced to a MCU with a hardware SPI port. Figure 6-1 depicts the operation shown in SPI Mode 0,0, which requires that the SCLK from the MCU idles in the `low' state, while Figure 6-2 shows the similar case of SPI Mode 1,1, where the clock idles in the `high' state. As is shown in Figure 6-1, the first byte transmitted to the A/D converter contains seven leading zeros before the start bit. Arranging the leading zeros this way induces the 10 data bits to fall in positions easily manipulated by the MCU. The MSB is clocked out of the A/D converter on the falling edge of clock number 14. Once the second eight clocks have been sent to the device, the MCU receive buffer will contain five unknown bits (the output is at high impedance for the first two clocks), the null bit and the highest order 2 bits of the conversion. Once the third byte has been sent to the device, the receive register will contain the lowest order eight bits of the conversion results. Employing this method ensures simpler manipulation of the converted data. Figure 6-2 shows the same thing in SPI Mode 1,1, which requires that the clock idles in the high state. As with mode 0,0, the A/D converter outputs data on the falling edge of the clock and the MCU latches data from the A/D converter in on the rising edge of the clock. 2002 Microchip Technology Inc. DS21295B-page 17 MCP3004/3008 CS SCLK MCU latches data from A/D converter on rising edges of SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DIN Data is clocked out of A/D converter on falling edges SGL/ D2 D1 DO Start DIFF HI-Z NULL BIT B9 B8 Don't Care DOUT B7 B6 B5 B4 B3 B2 B1 B0 Start MCU Transmitted Data Bit (Aligned with falling 0 0 0 0 00 01 edge of clock) MCU Received Data (Aligned with rising ? ? ? ? ? ? ? ? edge of clock) Data stored into MCU receive register after transmission of first 8 bits SGL/ DIFF D2 D1 DO X ? ? ? ? X X X X X X X X X X X 0 ? (Null) B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data stored into MCU receive register after transmission of last 8 bits X = "Don't Care" Bits Data stored into MCU receive register after transmission of second 8 bits FIGURE 6-1: SPI Communication with the MCP3004/3008 using 8-bit segments (Mode 0,0: SCLK idles low). CS SCLK MCU latches data from A/D converter on rising edges of SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Data is clocked out of A/D converter on falling edges DIN HI-Z Start Bit 0 ? ? 0 ? 0 ? 0 ? 0 ? 0 ? 1 ? SGL/ DIFF D2 Start SGL/ D2 D1 DO DIFF Don't Care NULL BIT B9 DOUT MCU Transmitted Data (Aligned with falling 0 edge of clock) MCU Received Data (Aligned with rising edge of clock) B8 B7 B6 B5 B4 B3 B2 B1 B0 D1 DO X ? ? ? X X X X X X X X X X X ? ? 0 (Null) B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data stored into MCU receive register after transmission of last 8 bits X = "Don't Care" Bits Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits FIGURE 6-2: SPI Communication with the MCP3004/3008 using 8-bit segments (Mode 1,1: SCLK idles high). DS21295B-page 18 2002 Microchip Technology Inc. MCP3004/3008 6.2 Maintaining Minimum Clock Speed VDD 4.096V Reference 0.1 F MCP1541 MCP601 + - 10 F 1 F 1 F When the MCP3004/3008 initiates the sample period, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample capacitor while the conversion is taking place. At 85C (worst case condition), the part will maintain proper charge on the sample capacitor for at least 1.2 ms after the sample period has ended. This means that the time between the end of the sample period and the time that all 10 data bits have been clocked out must not exceed 1.2 ms (effective clock frequency of 10 kHz). Failure to meet this criterion may introduce linearity errors into the conversion outside the rated specifications. It should be noted that during the entire conversion cycle, the A/D converter does not require a constant clock speed or duty cycle, as long as all timing specifications are met. VIN R1 C1 R2 C2 IN+ V REF MCP3004 IN- R3 R4 FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a second order anti-aliasing filter for the signal being converted by the MCP3004. 6.4 Layout Considerations 6.3 Buffering/Filtering the Analog Inputs If the signal source for the A/D converter is not a low impedance source, it will have to be buffered or inaccurate conversion results may occur (see Figure 4-2). It is also recommended that a filter be used to eliminate any signals that may be aliased back in to the conversion results, as is illustrated in Figure 6-3, where an op amp is used to drive, filter and gain the analog input of the MCP3004/3008. This amplifier provides a low impedance source for the converter input, plus a low pass filter, which eliminates unwanted high frequency noise. Low pass (anti-aliasing) filters can be designed using Microchip's free interactive FilterLabTM software. FilterLab will calculate capacitor and resistors values, as well as determine the number of poles that are required for the application. For more information on filtering signals, see AN699, "Anti-Aliasing Analog Filters for Data Acquisition Systems". When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 1 F is recommended. Digital and analog traces should be separated as much as possible on the board, with no traces running underneath the device or bypass capacitor. Extra precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing VDD connections to devices in a "star" configuration can also reduce noise by eliminating return current paths and associated errors (see Figure 6-4). For more information on layout tips when using A/D converters, refer to AN688, "Layout Tips for 12-Bit A/D Converter Applications". VDD Connection Device 1 Device 4 Device 3 Device 2 FIGURE 6-4: VDD traces arranged in a `Star' configuration in order to reduce errors caused by current return paths. 2002 Microchip Technology Inc. DS21295B-page 19 MCP3004/3008 6.5 Utilizing the Digital and Analog Ground Pins The MCP3004/3008 devices provide both digital and analog ground connections to provide additional means of noise reduction. As is shown in Figure 6-5, the analog and digital circuitry is separated internal to the device. This reduces noise from the digital portion of the device being coupled into the analog portion of the device. The two grounds are connected internally through the substrate which has a resistance of 5 -10. If no ground plane is utilized, both grounds must be connected to VSS on the board. If a ground plane is available, both digital and analog ground pins should be connected to the analog ground plane. If both an analog and a digital ground plane are available, both the digital and the analog ground pins should be connected to the analog ground plane. Following these steps will reduce the amount of digital noise from the rest of the board being coupled into the A/D converter. VDD MCP3004/08 Digital Side -SPI Interface -Shift Register -Control Logic Analog Side -Sample Cap -Capacitor Array -Comparator Substrate 5 - 10 DGND AGND 0.1 F Analog Ground Plane FIGURE 6-5: Ground Pins. Separation of Analog and Digital DS21295B-page 20 2002 Microchip Technology Inc. MCP3004/3008 7.0 7.1 PACKAGING INFORMATION Package Marking Information 14-Lead PDIP (300 mil) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN MCP3004-I/P 0212027 14-Lead SOIC (150 mil) Example: XXXXXXXXXXX XXXXXXXXXXX YYWWNNN MCP3004ISL XXXXXXXXXXX 0212027 14-Lead TSSOP (4.4mm) * Example: XXXXXXXX YYWW NNN 3004 I212 027 * Please contact Microchip Factory for B-Grade TSSOP devices Legend: XX...X YY WW NNN Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. 2002 Microchip Technology Inc. DS21295B-page 21 MCP3004/3008 Package Marking Information (Continued) 16-Lead PDIP (300 mil) (MCP3308) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN MCP3008-I/P 0212030 16-Lead SOIC (150 mil) (MCP3308) Example: XXXXXXXXXXXXX XXXXXXXXXXXXX YYWWNNN MCP3008-I/SL XXXXXXXXXX 0212030 DS21295B-page 22 2002 Microchip Technology Inc. MCP3004/3008 14-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A A2 c eB A1 B1 B p L Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width E1 .240 .250 .260 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .310 .370 .430 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 Units Dimension Limits n p MIN INCHES* NOM 14 .100 .155 .130 MAX MIN MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MAX 4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15 2002 Microchip Technology Inc. DS21295B-page 23 MCP3004/3008 14-Lead Plastic Small Outline (SL) - Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h 45 c A A2 L Units Dimension Limits n p A A2 A1 E E1 D h L c B INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12 MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12 A1 MIN MAX MIN MAX Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic .053 .052 .004 .228 .150 .337 .010 .016 0 .008 .014 0 0 .069 .061 .010 .244 .157 .347 .020 .050 8 .010 .020 15 15 1.75 1.55 0.25 6.20 3.99 8.81 0.51 1.27 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 DS21295B-page 24 2002 Microchip Technology Inc. MCP3004/3008 14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm (TSSOP) E E1 p D 2 n B 1 A c L A1 A2 Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D L c B1 MIN INCHES NOM 14 .026 .035 .004 .251 .173 .197 .024 4 .006 .010 5 5 MAX MIN .033 .002 .246 .169 .193 .020 0 .004 .007 0 0 .043 .037 .006 .256 .177 .201 .028 8 .008 .012 10 10 MILLIMETERS* NOM MAX 14 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 4.90 5.00 5.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 2002 Microchip Technology Inc. DS21295B-page 25 MCP3004/3008 16-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n E 1 A A2 c eB A1 B1 B Units Dimension Limits n p INCHES* NOM 16 .100 .140 .155 .115 .130 .015 .300 .313 .240 .250 .740 .750 .125 .130 .008 .012 .045 .058 .014 .018 .310 .370 5 10 5 10 p MILLIMETERS NOM 16 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 .036 0.46 7.87 9.40 5 10 5 10 L MIN MAX MIN MAX Number of Pins Pitch Top to Seating Plane A .170 Molded Package Thickness .145 A2 Base to Seating Plane A1 Shoulder to Shoulder Width E .325 Molded Package Width E1 .260 Overall Length D .760 Tip to Seating Plane L .135 c Lead Thickness .015 Upper Lead Width B1 .070 Lower Lead Width B .022 eB Overall Row Spacing .430 Mold Draft Angle Top 15 Mold Draft Angle Bottom 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-017 4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15 DS21295B-page 26 2002 Microchip Technology Inc. MCP3004/3008 16-Lead Plastic Small Outline (SL) - Narrow 150 mil (SOIC) E E1 p D 2 B n 1 h 45 c A A2 L Units Dimension Limits n p A A2 A1 E E1 D h L c B INCHES* NOM 16 .050 .053 .061 .052 .057 .004 .007 .228 .237 .150 .154 .386 .390 .010 .015 .016 .033 0 4 .008 .009 .013 .017 0 12 0 12 MILLIMETERS NOM 16 1.27 1.35 1.55 1.32 1.44 0.10 0.18 5.79 6.02 3.81 3.90 9.80 9.91 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.33 0.42 0 12 0 12 A1 MIN MAX MIN MAX Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic .069 .061 .010 .244 .157 .394 .020 .050 8 .010 .020 15 15 1.75 1.55 0.25 6.20 3.99 10.01 0.51 1.27 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-108 2002 Microchip Technology Inc. DS21295B-page 27 MCP3004/3008 NOTES: DS21295B-page 28 2002 Microchip Technology Inc. MCP3004/008 ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape(R) or Microsoft(R) Internet Explorer. Files are also available for FTP download from our FTP site. SYSTEMS INFORMATION AND UPGRADE HOT LINE The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive the most current upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. 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To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: MCP3004/008 Questions: 1. What are the best features of this document? Y N Literature Number: DS21295B FAX: (______) _________ - _________ 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21295B-page30 2002 Microchip Technology Inc. MCP3004/3008 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package Examples: a) b) Device: MCP3004: 4-Channel 10-Bit Serial A/D MCP3004T: 4-Channel 10-Bit Serial A/D (Tape and Reel) MCP3008: 8-Channel 10-Bit Serial A/D MCP3008T: 8-Channel 10-Bit Serial A/D (Tape and Reel) I P SL ST = -40C to +85C Converter Converter Converter Converter MCP3004-I/P: Industrial Temperature, PDIP package. MCP3004-I/SL: Industrial Temperature, SOIC package. MCP3004-I/ST: Industrial Temperature, TSSOP package. MCP3004T-I/ST: Industrial Temperature, TSSOP package, Tape and Reel. MCP3008-I/P: Industrial Temperature, PDIP package. MCP3008-I/SL: Industrial Temperature, SOIC package. c) d) a) Temperature Range: Package: b) = Plastic DIP (300 mil Body), 14-lead, 16-lead = Plastic SOIC (150 mil Body), 14-lead, 16-lead = Plastic TSSOP (4.4mm), 14-lead Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2002 Microchip Technology Inc. DS21295B-page31 MCP3004/3008 NOTES: DS21295B-page 32 2002 Microchip Technology Inc. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, KEELOQ, MPLAB, PIC, PICmicro, PICSTART and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro (R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. 2002 Microchip Technology Inc. DS21295B - page 33 M WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com ASIA/PACIFIC Australia Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Japan Microchip Technology Japan K.K. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Rocky Mountain 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-4338 China - Beijing Microchip Technology Consulting (Shanghai) Co., Ltd., Beijing Liaison Office Unit 915 Bei Hai Wan Tai Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934 Atlanta 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850 Boston 2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821 China - Chengdu Microchip Technology Consulting (Shanghai) Co., Ltd., Chengdu Liaison Office Rm. 2401, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-86766200 Fax: 86-28-86766599 Taiwan Microchip Technology (Barbados) Inc., Taiwan Branch 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 Chicago 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Dallas 4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924 China - Fuzhou Microchip Technology Consulting (Shanghai) Co., Ltd., Fuzhou Liaison Office Unit 28F, World Trade Plaza No. 71 Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521 Detroit Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260 EUROPE Austria Microchip Technology Austria GmbH Durisolstrasse 2 A-4600 Wels Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 China - Shanghai Microchip Technology Consulting (Shanghai) Co., Ltd. Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 Kokomo 2767 S. Albright Road Kokomo, Indiana 46902 Tel: 765-864-8360 Fax: 765-864-8387 Denmark Microchip Technology Nordic ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910 Los Angeles 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338 China - Shenzhen Microchip Technology Consulting (Shanghai) Co., Ltd., Shenzhen Liaison Office Rm. 1315, 13/F, Shenzhen Kerry Centre, Renminnan Lu Shenzhen 518001, China Tel: 86-755-2350361 Fax: 86-755-2366086 New York 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335 France Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 China - Hong Kong SAR Microchip Technology Hongkong Ltd. Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Germany Microchip Technology GmbH Steinheilstrasse 10 D-85737 Ismaning, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Toronto 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509 India Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 Italy Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 United Kingdom Microchip Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 08/01/02 DS21295B-page 34 2002 Microchip Technology Inc. |
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